Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices

This work explores the effect of adding a new partitioning step into the traditional complex programmable logic device (CPLD) CAD flow. A novel algorithm based on Rent’s rule and simulated annealing partitions a design before it enters the place and route stage in CPLD CAD. The resulting partitions are then placed using an enhanced placement tool. Experiments conducted on Altera’a APEX20K chips indicate that a partitioned placement can provide an average performance gain of 7% over flat placements.